1. Field of the Invention
The present invention relates to a method for generating mask data, a mask, a computer readable recording medium, and more particularly a method for generating mask data, a mask, a computer readable recording medium, for forming trench isolation regions.
2. Description of Related Art
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements in a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique will be described below.
FIGS. 18(a)-18(c) show in cross-section steps of forming trench isolation regions using a conventional trench isolation technique.
FIG. 18(a) shows a silicon substrate 110 having trenches 116, and a dielectric layer 121 formed over the silicon substrate 110. A polishing stopper layer 114 is formed over effective convex regions 130 of the silicon substrate 110. A pad layer 112 is interposed between the effective convex regions 130 and the polishing stopper layer 114.
As shown in FIG. 18(b), the dielectric layer 121 is planarized using the polishing stopper layer 114 as a stopper. The planarization of the dielectric layer 121 is performed by a chemical-mechanical polishing method (hereinafter referred to as a xe2x80x9cCMP methodxe2x80x9d).
Then, as shown in FIG. 18(c), the polishing stopper layer 114 is removed to thereby form trench dielectric layers 120, whereby trench isolation regions 124 are completed.
However, as shown in FIG. 18(b), a device design may require that plural effective convex regions 130 are closely formed in one area and an isolated effective convex region 130 is formed separated from such area. In this case, the following problems occur.
When the dielectric layer 121 is planarized by the CMP method, the polishing stopper layer 114 at the isolated effective convex region 130 may be excessively cut. On the other hand, the polishing stopper layer 114 on the densely formed effective convex regions 130 may not be cut enough as compared to the polishing stopper layer 114 at the isolated effective convex region 130. This phenomenon occurs because the polishing rate differs depending on pattern densities of the effective convex regions 130. In other words, a polishing pressure is concentrated on the polishing stopper layer 114 at the isolated effective convex region 130. As a result, the polishing rate at the isolated effective convex region 130 becomes greater than the polishing rate at the densely formed effective convex regions 130. Consequently, the polishing stopper layer 114 at the isolated effective convex region 130 is excessively polished.
When the polishing stopper layer 114 at the isolated effective convex region 130 is excessively polished, the thickness of the resultant trench dielectric layer 120 becomes irregular, as shown in FIG. 18(c). Also, the polishing stopper layer 114 cannot properly perform its function. Moreover, as the isolated effective convex region 130 is excessively polished, the polishing cloth warps, and erosion occurs in the polishing stopper layer 114 in the area where the effective convex regions 130 are densely formed. The erosion is a phenomenon in which a corner section 114a of the polishing stopper layer 114 is cut. Also, when the polishing cloth warps, dishing occurs in an upper portion of the dielectric layer 121. The dishing is a phenomenon in which an upper portion of the dielectric layer 121 is formed in a dish shape.
In order to solve the problems described above, one technique, in which dummy convex regions 132 are formed in the trench 116, as shown in FIG. 19, is proposed. By the provision of the dummy convex regions 132, the polishing pressure is distributed on the dummy convex regions 132. Accordingly, the concentration of the polishing pressure on the isolated effective convex region 130 is prevented, and the polishing rate at the same region does not become excessively greater. Consequently, by the provision of the dummy convex regions 132, the isolated effective convex region 130 is prevented from being excessively cut.
The technique for forming the dummy convex regions 132 is described in Japanese laid-open patent application HEI 9-107028, Japanese laid-open patent application HEI 9-181159, Japanese laid-open patent application HEI 10-92921, Japanese laid-open patent application HEI 11-26576, U.S. Pat. No. 5,885,856 and U.S. Pat. No. 5,902,752.
It is an object of the present invention to provide a method for generating mask data, a mask, and a computer readable recording medium, which are used for forming dummy convex regions in a specified pattern in a trench isolation region.
(A) In accordance with a first embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device has a trench isolation region, provided in a semiconductor substrate, defining a row direction and first virtual linear lines extending in a direction that traverses the row direction, and a plurality of dummy convex regions provided in the trench isolation region, wherein the row direction and the first virtual linear lines define an angle of 2 to 40 degrees, and the dummy convex regions are disposed on the first virtual linear lines. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d used here refers to one direction that is virtually defined in consideration of, for example, a restriction region.
In accordance with the present invention, for example, the following two effects are achieved.
(1) In accordance with the first embodiment of the present invention, the dummy patterns are set such that the dummy convex regions are disposed on the first virtual linear lines. The row direction and the first virtual linear lines define an angle of 2 to 40 degrees. In other words, the dummy patterns are set such that adjacent ones of the dummy convex regions formed on the first virtual linear lines and disposed next to one another in the row direction are mutually offset in a column direction. Accordingly, the adjacent dummy patterns disposed in the row direction are mutually offset in the column direction. As a result, in step (c), the dummy patterns can be readily set at a high level of density in an area adjacent to a restriction region pattern that extends in the row direction. In other words, even when some of the dummy patterns overlap the restriction region pattern, the other dummy patterns are securely generated in an area adjacent to the restriction region pattern. As a consequence, dummy patterns can be securely provided in a region where a gap between adjacent restriction region patterns is narrow. As a result, the following effects are achieved.
When dummy convex regions are formed in a trench, the dummy convex regions can be securely disposed in an area adjacent to the restriction regions. As a consequence, when the dielectric layer filled in the trench is polished, the polishing pressure is securely distributed on the dummy convex regions adjacent to the restriction region.
(2) Also, in accordance with the present invention, the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded. As a result, the generation of pattern skipping of dummy convex regions or scratches during polishing of the dielectric layer can be securely prevented, as described below in detail.
The first virtual linear lines may preferably be spaced a specified gap from one another. In one embodiment, the gap may preferably be 1-16 xcexcm.
A center of each of the dummy convex regions may preferably be located on each of the first virtual linear lines.
(B) In accordance with a second embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device, the semiconductor device comprising a trench isolation region, provided in a semiconductor substrate, defining a column direction and second virtual linear lines extending in a direction that traverses the column direction, and a plurality of dummy convex regions provided in the trench isolation region, wherein the column direction and the second virtual linear lines define an angle of 2 to 40 degrees, and the dummy convex regions are disposed on the second virtual linear lines. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9ccolumn directionxe2x80x9d used here refers to one direction that perpendicularly traverses the row direction and is virtually defined in consideration of, for example, a restriction region.
In accordance with the present invention, for example, the following two effects are achieved.
(1) In accordance with the second embodiment of the present invention, the dummy patterns are set such that the dummy convex regions are disposed on the second virtual linear lines. The column direction and the second virtual linear lines define an angle of 2 to 40 degrees. In other words, the dummy patterns are set such that adjacent ones of the dummy convex regions formed on the second virtual linear lines and disposed next to one another in the column direction are mutually offset in the row direction. Accordingly, the adjacent dummy patterns disposed in the column direction are mutually offset in the row direction. As a result, in step (c), the dummy patterns can be readily set at a high level of density in an area adjacent to a restriction region pattern that extends in the column direction. In other words, even when some of the dummy patterns overlap the restriction region pattern, the other dummy patterns are securely generated in an area adjacent to the restriction region pattern. As a consequence, dummy patterns can be securely provided in a region where a gap between adjacent restriction region patterns is narrow. As a result, the effect (1) described above in conjunction with the method for generating mask data of the first embodiment can be achieved.
(2) In accordance with the second embodiment of the present invention, the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded. As a result, the effect (2) described above in conjunction with the method for generating mask data of the first embodiment can be achieved.
Also, the method for generating mask data in accordance with the first embodiment and the method for generating mask data in accordance with the second embodiment may be combined. By the method for generating mask data in accordance with the combined embodiments, dummy convex regions can be more securely formed in areas adjacent to restriction regions.
In the method for generating mask data in accordance with the second embodiment of the present invention, the second virtual linear lines may preferably be spaced a specified gap from one another. The gap may preferably be 1-16 xcexcm.
A center of each of the dummy convex regions may preferably be located on each of the second virtual linear lines.
In the method for generating mask data in accordance with the first embodiment or the second embodiment, the dummy convex regions may be formed in any one of the following manners:
(1) A plan area of the dummy convex regions is about 30-50% of a plan area of the trench isolation region. As a result, the polishing pressure can be effectively distributed on the dummy convex regions. In a preferred embodiment, the plan area of the dummy convex regions may be 40% of the plan area of the trench isolation region.
(2) Each of the dummy convex regions may have a generally rectangular shape in plan view. In other words, when the trench region formed in the silicon substrate is viewed from above, each of the dummy convex regions may have a generally rectangular shape. The formation of a dummy convex region in a generally rectangular shape is relatively easy. Preferably, each of the dummy convex regions may have a generally square shape. By forming the dummy convex regions in a generally square shape, the dummy convex regions can be more densely formed. For example, the dummy convex regions can be more securely formed in an area adjacent to a cross point where restriction regions cross one another. As a result, the dummy convex regions can be more effectively formed in an area adjacent to a restriction region with a complex pattern (for example, a prohibited area around a gate region that is formed with a complex pattern).
(3) When each of the dummy convex regions has a rectangular shape in plan (i.e., as viewed from above), adjacent ones of the dummy convex regions disposed on the first virtual linear line or adjacent ones of the dummy convex regions disposed on the second virtual linear line have sides that partially oppose to one another as viewed from above. In a preferred embodiment, the sides of the adjacent ones of the dummy convex regions are spaced a distance from one another, wherein the distance may preferably be shorter than each of the sides of each of the dummy convex regions. Preferably, the distance between the sides may be about 0.5-5 xcexcm. More preferably, the distance between the sides may be about 1 xcexcm.
(4) When the plan configuration of each of the dummy convex regions is rectangular, each side of each of the dummy convex regions may preferably have a length of 1 xcexcm or greater. When each side of each of the dummy convex regions is 1 xcexcm long or greater, the amount of data for generating masks which is used to form the dummy convex regions does not substantially increase.
In a preferred embodiment, each side of each of the dummy convex regions has a length of 10 xcexcm or shorter. In a more preferred embodiment, each side of each of the dummy convex regions has a length of 5 xcexcm or shorter. When each side of each of the dummy convex regions is 5 xcexcm long or shorter, a dielectric layer deposited over the dummy convex regions is prevented from getting thicker when the dielectric layer is embedded in the trench. Accordingly, the dummy convex regions having sides that have a length of 5 xcexcm or shorter are particularly preferable when a dielectric layer is embedded in a trench using a high-density plasma CVD.
In a more preferred embodiment, each side of each of the dummy convex regions has a length of about 2 xcexcm.
(C) In accordance with a third embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device has a trench isolation region, provided in a semiconductor substrate, defining a row direction and a column direction and a plurality of dummy convex regions in the trench isolation region disposed in the row direction and the column direction. Each of the dummy convex regions has a generally square shape in plan. The dummy convex regions that are disposed in the row direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy convex regions. The dummy convex regions that are disposed in the row direction are offset by a second distance from one another in the column direction, the second distance being about a half of a side of each of the dummy convex regions. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d and the xe2x80x9ccolumn directionxe2x80x9d may be defined in a similar manner as the first and second embodiments.
In accordance with the third embodiment of the present invention, the adjacent dummy patterns disposed in the row direction are mutually offset in the column direction. As a result, the method for generating mask data in accordance with the third embodiment of the present invention provides the same effects achieved by the method for generating mask data in accordance with the first embodiment of the present invention.
(D) In accordance with a third embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device comprising a trench isolation region, provided in a semiconductor substrate, defining a row direction and a column direction and a plurality of dummy convex regions in the trench isolation region disposed in the row direction and the column direction, wherein each of the dummy convex regions has a generally square shape in plan, the dummy convex regions that are disposed in the column direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy convex regions, and the dummy convex regions that are disposed in the column direction are offset by a second distance from one another in the row direction, the second distance being about a half of a side of each of the dummy convex regions. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d and the xe2x80x9ccolumn directionxe2x80x9d may be defined in a similar manner as the first and second embodiments.
In accordance with the fourth embodiment of the present invention, the adjacent dummy patterns disposed in the column direction are mutually offset in the row direction. As a result, the method for generating mask data in accordance with the fourth embodiment of the present invention provides the same effects achieved by the method for generating mask data in accordance with the second embodiment of the present invention.
Also, the method for generating mask data in accordance with the third embodiment and the method for generating mask data in accordance with the fourth embodiment may be combined. By the method for generating mask data in accordance with the combined embodiments, dummy convex regions can be more securely formed in areas adjacent to restriction regions.
In the semiconductor device manufactured by the method in accordance with the third embodiment or the fourth embodiment, each side of each of the dummy convex regions may preferably have a length of about 2 xcexcm.
In any one of the methods for generating mask data in accordance with the first through fourth embodiments of the present invention, the restriction region includes, for example, an effective region and a prohibited area. The effective region may include, for example, an active region, a gate region, a well region formed to function as a resistance and a boundary region between an n-well and a p-well.
(E) In accordance with a fifth embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device has a trench isolation region provided in a semiconductor substrate and a plurality of dummy convex regions provided in the trench isolation region. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions, and defining a row direction and first virtual linear lines extending in a direction that traverses the row direction, wherein the row direction and the first virtual linear lines define an angle of 2 to 40 degrees, and the dummy convex regions are disposed on the first virtual linear lines; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d used here refers to one direction that is virtually defined in consideration of, for example, a restriction region pattern.
In accordance with the fifth embodiment of the present invention, the dummy patterns are formed to be disposed on the first virtual linear lines. The row direction and the first virtual linear lines define an angle of 2 to 40 degrees. In other words, adjacent ones of the dummy patterns that are formed on the same first virtual linear line and disposed in the row direction are mutually offset in a column direction. As a result, the dummy patterns can be readily disposed at a high level of density in an area adjacent to the restriction region pattern that extends in the row direction. In other words, even when some of the dummy patterns overlap the restriction region pattern, the other dummy patterns in an area adjacent to the restriction region pattern are securely disposed. As a consequence, the dummy convex regions can be securely formed in a region adjacent to the restriction region. As a result, polishing pressure can be securely distributed on the dummy convex regions adjacent to the restriction regions when the dielectric layer filled in the trench is polished. Also, since the dummy patterns can be securely disposed in an area adjacent to the restriction regions, the dummy patterns can also be securely provided in a region where a gap between the adjacent restriction region patterns is narrow.
Also, the fifth embodiment of the present invention can achieve the effect (2) that is obtained by the method for generating mask data in accordance with the first embodiment.
(F) In accordance with a sixth embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device has a trench isolation region provided in a semiconductor substrate and a plurality of dummy convex regions provided in the trench isolation region. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions, and defining a column direction and second virtual linear lines extending in a direction that traverses the column direction, wherein the column direction and the second virtual linear lines define an angle of 2 to 40 degrees, and the dummy convex regions are disposed on the second virtual linear lines; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9ccolumn directionxe2x80x9d used here refers to one direction that perpendicularly traverses the row direction and is virtually defined in consideration of, for example, a restriction region.
In accordance with the sixth embodiment of the present invention, the dummy patterns are formed to be disposed on the second virtual linear lines. The column direction and the second virtual linear lines define an angle of 2 to 40 degrees. In other words, adjacent ones of the dummy patterns that are formed on the same second virtual linear line and disposed in the column direction are mutually offset in the row direction. As a result, the dummy patterns can be readily disposed at a high level of density in an area adjacent to the restriction region pattern that extends in the column direction. In other words, even when some of the dummy patterns overlap the restriction region pattern, the other dummy patterns in an area adjacent to the restriction region pattern are securely disposed. As a consequence, the dummy convex regions can be securely formed in a region adjacent to the restriction region. As a result, the dummy convex regions can be securely formed in an area adjacent to the restriction regions. As a consequence, when the dielectric layer filled in the trench is polished, the polishing pressure is securely distributed on the dummy convex regions adjacent to the restriction regions.
Also, since the dummy patterns can be securely disposed in an area adjacent to the restriction regions, the dummy patterns can also be securely provided in a region where a gap between the adjacent restriction region patterns is narrow.
Also, the sixth embodiment of the present invention can achieve the effect (2) that is achieved by the method for generating mask data in accordance with the first embodiment.
Also, the method for generating mask data in accordance with the fifth embodiment and the method for generating mask data in accordance with the sixth embodiment may be combined. By the method for generating mask data in accordance with the combined embodiments, dummy patterns can be more securely formed in areas adjacent to restriction region patterns.
(G) In accordance with a seventh embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device, wherein the semiconductor device has a trench isolation region provided in a semiconductor substrate defining a row direction and a column direction and a plurality of dummy convex regions in the trench isolation region disposed in the row direction and the column direction. Placement of the plurality of dummy convex regions may be determined by a method including the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions, wherein each of the dummy convex regions has a generally square shape in plan, the dummy convex regions that are disposed in the row direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy convex regions, and the dummy convex regions that are disposed in the row direction are offset by a second distance from one another in the column direction, the second distance being about a half of a side of each of the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d and the xe2x80x9ccolumn directionxe2x80x9d may be defined in a similar manner as the fifth and sixth embodiments.
In accordance with the seventh embodiment of the present invention, the adjacent dummy patterns disposed in the row direction are mutually offset in the column direction. As a result, the method for generating mask data in accordance with the seventh embodiment of the present invention provides the same effects achieved by the method for generating mask data in accordance with the fifth embodiment of the present invention.
(H) In accordance with an eighth embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device, wherein the semiconductor device has a trench isolation region provided in a semiconductor substrate defining a row direction and a column direction and a plurality of dummy convex regions in the trench isolation region disposed in the row direction and the column direction. Placement of the plurality of dummy convex regions may be determined by a method including the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions, wherein each of the dummy convex regions has a generally square shape in plan, the dummy convex regions that are disposed in the column direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy convex regions, and the dummy convex regions that are disposed in the column direction are offset by a second distance from one another in the row direction, the second distance being about a half of a side of each of the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The xe2x80x9crow directionxe2x80x9d and the xe2x80x9ccolumn directionxe2x80x9d may be defined in a similar manner as the fifth and sixth embodiments.
In accordance with the eighth embodiment of the present invention, the adjacent dummy patterns disposed in the same column direction are mutually offset in the row direction. As a result, the method for generating mask data in accordance with the eighth embodiment of the present invention provides the same effects achieved by the method for generating mask data in accordance with the sixth embodiment of the present invention.
Also, the method for generating mask data in accordance with the seventh embodiment and the method for generating mask data in accordance with the eighth embodiment may be combined. By the method for generating mask data in accordance with the combined embodiments, dummy patterns can be more securely formed in areas adjacent to restriction region patterns.
The method for generating mask data in accordance with any one of the fifth embodiment through the eighth embodiment may have any one of the following embodiments:
The restriction region includes an effective region and a prohibited area provided around the effective region, and the step (a) includes the steps of (a-1) setting an effective region pattern that defines the effective region and (a-2) setting a prohibited area pattern that defines the prohibited area about the effective region pattern.
The effective region may include an active region pattern, a gate region pattern, an impurity diffusion region pattern formed to function as a resistance and a boundary region pattern between an n-well and a p-well.
The method may further include, before step (c), step (d) of reversing the restriction region pattern. By the inclusion of step (d), the restriction region pattern and the dummy patterns can be easily mixed.
A mask in accordance with one embodiment of the present invention can be formed by the method for generating mask data described above.
By the use of the mask in accordance with the present invention in a method for manufacturing a semiconductor device, dummy convex regions can be securely formed in an area adjacent to restriction regions.
A computer readable recording medium in accordance with the present invention stores mask data obtained by the method for generating mask data according to any one of the embodiments described above.
A mask of the present invention can be formed based on the data stored in the computer readable recording medium in accordance with the present invention.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings that illustrate, by way of example, various features of embodiments of the invention.